Microsoft CEO Dumps Half of Shares Ahead of Capital Gains Tax Change

Microsoft teases design overhaul of major Windows 11 app

Microsoft teased a design overhaul that is coming to the Windows 11 File Explorer app in a future update at its Build developer conference this week.

The new File Explorer design is based on WinUI 3 and will modernize the app’s folders, sidebar, address bar, and search bar to be more in tune with the overall Windows 11 style. This will bring to File Explorer a look and feel with more rounded and blurred designs, as well as mouse and touch optimizations, Windows Central noted.

Microsoft initially made small updates to File Explorer in Windows 11 and continually so in 2022, adding such features as tabs. Still, the legacy design of the app remained from years ago. The updated app is featured in a reel alongside functionalities for Microsoft’s Copilot app, in which you can see the notable differences in the File Explorer design, such as the action buttons being located below the address bar.

The brand is also said to be working on a Gallery feature that will get the same update to the WinUI 3 modern design as File Explorer.

Windows Insiders are currently testing other app updates, such as pane view, but not the updated File Explorer design. This is a feature that connects to Microsoft 365 and “shows recent activity on shared files, and even provides contextual information like where the file came from,” such as email or chat, according to Windows Central.

Since the File Explorer design update was inadvertently shown, users might have to wait a little longer for Insider testing and a general rollout.

Still, this update is sure to excite Windows enthusiasts who have long desired a new look for the File Explorer app. Many expected to have to wait until Windows 12 to see a real change. One such Microsoft fan earlier this month showcased his own concept of the upcoming Windows 12 system with a redesigned File Explorer featuring unique functions to match the updated look.

Smart Wave Dump - A smart way to generate waveforms

By Navdeep Patel, Nikunj Naliyapara (eInfochips, an Arrow Company)

1- Introduction

As an engineer, be it design or verification, more than half of our time is spent in debugging and analysis. One of the most common and basic approach to that is using the waveform that shows the behavior of the signals. It is very likely that we are aware about how to dump such waveforms and observe the behavior of the signals we are interested in, but majority of the time, we also dump much more than what we need. We can ignore the signals that are not of interest to us in the recording, but here we should note that if we do not generate the waves properly then, we may face some disadvantages or challenges compared to ‘Smart Wave Dump (SWD)’.

eInfochips’ SWD provides several advantages over traditional waveform generation methods. Some of the advantages are faster simulation, smaller waveform files, faster execution of waveform analyzer tool, etc.

One of the main advantages of SWD is, it is tool and project agnostic. It supports Cadence, Synopsys and Mentor Graphics tools and it is reusable across different projects. Therefore, SWD is a generic solution to generate waveforms. Here at eInfochips, we have used SWD in multiple projects with different tools.

SWD supports features like, save the waveform database as per scope or hierarchy, dumping the waves in specific time range, store delta cycle values or value change sequence in the waveform database and many more. Details about the same will be provided in upcoming sections.

So, let us look further into next sections and understand more about SWD.

2- About SWD

SWD comprises system tasks from SystemVerilog LRM and user guides of various simulation tools. Therefore, user just needs to include the SWD package in the Testbench and then can use it with help of a set of predefined command line switches. Such predefined command line switches are used to control the waveform generation for various nodes (in/out signals, memories, objects declared in task and function scopes, etc.), various scopes (hierarchical instantiations) and other supported set of features.

SWD supports below mentioned features. We will look into more details for each of those in next section.

From above listed features, SWD is reusable across multiple projects for almost all features apart from scope / hierarchical dumping. Because, with different project there can be different hierarchy so, based on individual’s requirement user need to update the hierarchical paths for scope dumping. Upcoming sections have more detail on scope / hierarchical dumping.

3- Features Supported

SWD supports various features to generate the waveform database. Each feature has its own command line switch. User can use more than one feature at a time by using multiple command line switches. User can use various features of SWD package as per requirement and does not need to worry about various tool specific switches.

Supported features are as below:

SWD package can be used with multiple EDA tools but it is possible that support for mentioned features will vary as per tool vendor. So based on that, SWD supports the listed features for various tools as per below Table 1:

Table 1: SWD features support with different tools

In above Table 1,

“Yes” means SWD package supports that feature with given tool,

“No” means SWD package currently does not support that feature with given tool but the tool may or may not support the feature.

4- Scope / hierarchical dumping of SWD

Let us take an example to understand better scope / hierarchical dumping feature of SWD. A chip has multiple IPs/sub blocks and it might be possible that those IPs/blocks are divided across multiple engineers. Now, while debugging, we would be more interested in the assigned block and other blocks with which it interacts and so is the case for waveforms. Let us say we dump only the signals for which we are interested about and skip others. This can be achieved using scope dumping feature of SWD.

User can use Scope dumping feature to dump signals selectively from design and/or test-bench scopes.

There is one Scope Control Task in the SWD package. This task consists the list of scope dumping items with details of hierarchical paths and scope level. At starting of any new project, user need to do one time update for the hierarchical paths to support scope dumping. Then SWD package can be used with different tools throughout the project. Even this updating process is not required if user is using the SWD package for any derivative project.

Scope Control Task:

To understand more about the Scope Control task, please look into below Figure 1. There is a sample code of Scope Control Task of the SWD package.

Figure 1: Sample code of Scope Control Task

Scope Control Task has a macro “DUMP_COMP” that contains the tool specific or SV system tasks and logic that makes the SWD package generic and reusable across multiple tools. This macro takes two arguments, first one is the instance name (scope or hierarchy) and second one is the scope level.

There are two major supports provided for scope level,

For example,

Scope Control Task have one input argument, scope_profile_name. User can use this scope_profile_name in command line argument while running the testcase to specify which signals / hierarchies needs to be recorded for a specific testcase. Therefore, from Figure 1, if user uses scope_profile_name as “blk1” then, inputs, outputs and inouts value changes will be recorded for tb_top instance and, all signals’ value changes will be recorded for tb_top.blk_inst1 instance and all instantiations below tb_top.blk1_inst.

User can update this Scope Control Task by adding or removing or updating scope_profile_name cases inside the case statement and create as many as scope profiles required, along with various dumping scope within one scope profile.

This is highly recommended and very useful feature of SWD.

5- Flow to use SWD

Below Figure 2, explains flow for SWD usage:

Figure 2: Flow to use SWD

6- Tcl script based approach for SWD

Another approach for SWD is Tcl (Tool command language) based. If tool supports Tcl files for waveform generation then this approach can be used. Here, SWD package will contains Tcl scripts with procedures and system tasks from tool manuals.

This Tcl script based approach for SWD, also supports various features discussed in previous sections. Therefore, similarly, user can use the SWD Tcl package while running any testcase or regression along with appropriate command line switches.

For Scope / hierarchical dumping, there is one scope control procedure in the SWD package. This procedure consists the list of scope dumping items with details of hierarchical paths and scope level. Here, user can specify scope level (depth from specified scope/instance) as per requirement, which can be ‘0’, ‘1’,’2’, etc.

In below Figure 3, there is a sample code of Scope Control Procedure of the SWD Tcl package. A “set_scope_profile” procedure can be there to handle which signals / hierarchies needs to be recorded.

Figure 3: Sample code of scope control procedure in SWD Tcl package

User can update this Scope Control Procedure by adding or removing or updating ‘set_scope_profile’ and create as many scope profiles as required, along with various dumping scope within one scope profile.

One of the advantage of Tcl based approach is, it is compilation agnostic so, Tcl file can be updated and directly used with already compiled database snapshot in case required.

7- Advantages

Some of the main advantages of SWD are as below:

8- Example to demonstrate advantages of SWD

As mentioned, SWD can be helpful to improve simulation speed and save disk space. To demonstrate that, we have taken an example of Xcelium simulator from Cadence and tried some features of SWD.

This example is from one of the projects, which had around 15 digital blocks/IPs with reasonable complexities. We ran a sample test with below mentioned categories:

Below Figures 4 & 5, shows simulation run time and waveform file (database) size for above listed categories:

Figure 4: Run time and disk space storage for sample test with different features of SWD

The same three categories with delta cycle values dumping for the same sample test, please see below Figure 5 for the outcome:

Figure 5: Run time and disk space storage for sample test with different features of SWD and delta cycle dump

It is clear that with Scope Dump and Time Range Dump features of SWD, one can improve simulation speed (approx. 30% to 50% lesser simulation time) and save good amount of disk space.

9- Conclusion

We have seen that using SWD, how user can generate the waves and gain advantages like, faster simulation, better viewer performance, save the disk space, etc. and improve the overall project efficiency.

Using SWD, user can utilize time and disk space efficiently. Since SWD provide generic solution across multiple EDA tools, user need not to bother about different EDA tools specific switches and commands and can use SWD to gain various advantages as discussed. Efficiency plays major role and SWD helps to improve it. eInfochips, an Arrow company, is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. For more information connect with eInfochips today.”

References:

Authors:

Navdeep Patel: Navdeep Patel is working as a Senior ASIC Verification Engineer at eInfochips, an Arrow Company.

Nikunj Naliyapara: Nikunj Naliyapara is working as a Senior ASIC Verification Engineer at eInfochips, an Arrow Company.

If you wish to download a copy of this white paper, click here